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short form data sheet 82P33714 revision 1 10/20/14 1 ?2014 integrated device technology, inc. synchronous equipment timing source for synchronous ethernet 82P33714 highlights ? synchronous equipment timing source (sets) for synchronous ethernet (synce) per itu-t g.8264 ? dpll1 generates itu-t g.8262 compli ant synce clocks, telcordia gr-1244-core/gr-253-core , and itu-t g.813 compliant sonet/sdh clocks ? dpll2 performs rate conversions fo r synchronization interfaces or for other general purpose timing applications ? dpll1 can be configured as a digita lly controlled os cillators (dcos) for ptp clock synthesis ? dco frequency resolution is [(77760 / 1638400) * 2^-48] or ~1.686305041e-10 ppm ? apll1 and apll2 generate clocks with jitter < 1 ps rms (12 khz to 20 mhz) for: 1000base-t and 1000base-x ? fractional-n input dividers suppor t a wide range of reference fre- quencies ? locks to 1 pulse per second (pps) references ? dplls, apll1 and apll2 can be configured from an external eeprom after reset features ? differential reference inputs (in1 to in4) accept clock frequencies between 1 pps and 650 mhz ? single ended inputs (in5 to in6) accept reference clock frequencies between 1 pps and 162.5 mhz ? loss of signal (los) pins (los0 to los3) can be assigned to any clock reference input ? reference monitors qualify/disqua lify references depending on activ- ity, frequency and los pins ? automatic reference selection state machines select the active refer- ence for each dpll based on the reference monitors, priority tables, revertive and non-revertive settings and other programmable settings ? fractional-n input dividers enable the dplls to lock to a wide range of reference clock frequencies including: 10/100/1000 ethernet, 10g ethernet, otn, sonet/sdh, pdh, tdm, gsm, cpri, and gnss frequencies ? any reference inputs (in1 to in6) can be designated as external sync pulse inputs (1 pps, 2 khz, 4 khz or 8 khz) associated with a select- able reference clock input ? frsync_8k_1pps and mfrsync_2k_1pps output sync pulses that are aligned with the selected ex ternal input sync pulse input and frequency locked to the associated reference clock input ? dpll1 can be configured with bandwidths between 0.09 mhz and 567 hz ? dpll1 locks to input references with frequencies between 1 pps and 650 mhz ? dpll2 locks to input references with frequencies between 8 khz and 650 mhz ? dpll1 complies with itu-t g. 8262 for synchronous ethernet equip- ment clock (eec), and g.813 fo r synchronous equipment clock (sec); and telcordia gr-253-core / gr-1244-core for stratum 3 and sonet minimum clock (smc) ? dpll1 generates clocks with pdh, tdm, gsm, cpri/obsai, 10/ 100/1000 ethernet and gnss frequencies; these clocks are directly available on out1 and out8 ? dpll2 generates n x 8 khz clocks up to 100 mhz that are output on out9 and out10 ? apll1 and apll2 are connected to dpll1 ? apll1 and apll2 generate 10/100/1000 ethernet, 10g ethernet, or sonet/sdh frequencies ? any of eight common tcxo/ocxo frequencies can be used for the system clock: 10 mhz, 12.8 mhz, 13 mhz, 19.44 mhz, 20 mhz, 24.576 mhz, 25 mhz or 30.72 mhz ? the i2c slave, spi or the uart interface can be used by a host pro- cessor to access the control and status registers ? the i2c master interface can aut omatically load a device configura- tion from an external eeprom after reset ? differential outputs out3 to out6 output clocks with frequencies between 1 pps and 650 mhz ? single ended outputs out1, out2, out7 and out8 output clocks with frequencies between 1 pps and 125 mhz ? single ended outputs out9 and out10 output clocks n*8 khz multi- ples up to 100 mhz ? dpll1 supports independent programmable delays for each of in1 to in6; the delay for each input is programmable in steps of 0.61 ns with a range of ~78 ns ? the input to output phase delay of dpll1 is programmable in steps of 0.0745 ps with a total range of 20 s ? the clock phase of each of the output dividers for out1 (from apll1) to out8 is individually programmable in steps of ~200 ps with a total range of +/-180 ? 1149.1 jtag boundary scan ? 72-pin qfn green package applications ? access routers, edge routers, core routers ? carrier ethernet switches ? multiservice access platforms ?pon olt ? lte enodeb ? itu-t g.8264 synchronous equipment timing source (sets) ? itu-t g.8262 synchronous ethernet equipment clock (eec) ? itu-t g.813 synchronous equipment clock (sec) ? telcordia gr-253-core/gr1244-core stratum 3 clock (s3) and sonet minimum clock (smc)
82P33714 short form data sheet synchronous equipment timing source for synchronous ethernet i 2 revision 1 10/20/14 description the 82P33714 synchronous equipment timing source (sets) for sync hronous ethernet (synce) provides tools to manage timing refere nces, clock generation and timing paths for synce based clocks, per itu-t g.8264 and itu-t g.8262. 82P33714 meets the requirements of itu-t g.8262 for synchronous ethernet equipment clocks (eecs) and itu-t g.813 fo r synchronous equipment clocks (sec). the device outputs low -jitter clocks that can directly synchronize ethernet interf aces; as well as sonet/sdh and pdh interfaces. the 82P33714 accepts four differential reference inputs and two single ended reference inputs that can operate at common gnss, ethernet, sonet/sdh and pdh frequencies that range from 1 pulse per second ( pps) to 650 mhz. the references are continually monitored for loss of sig- nal and for frequency offset per us er programmed thresholds. all of the references are available to both digital plls (dplls). the active reference for each dpll is determined by forced selection or by automatic sele ction based on user programmed pr iorities and locking allowance s and based on the reference monitors and los inputs. the 82P33714 can accept a clock reference and an associated phase lock ed sync signal as a pair. dpll1 can lock to the clock ref erence and align the frame sync and multi-frame sync out puts with the paired sync input. the device allows any of the differential or sing le ended reference inputs to be configured as sync inputs that can be associated with any of the other differential or single ended reference inputs. the input sync signals can have a frequency of 1 pps, 2 khz, 4 khz or 8 khz. this featur e enables dpll1 to phase align its frame sync and multi-frame sync outputs with a sync input without the need use a low bandwidth setting to lock directly to the sync input. the dplls support three primary operating m odes: free-run, locked and holdover. in free- run mode the dplls synthesize clocks ba sed on the system clock alone. in locked mode the dplls filter reference clock jitter with the selected bandwidth. in locked mode, the long-term output fre- quency accuracy is the same as the long term frequency accuracy of the selected input reference. in holdover mode, the dpll use s frequency data acquired while in locked mode to generate accurate fr equencies when input refer ences are not available. dpll1 also supports dco mode. in dco mode the dpll control l oop is opened and the dco can be controlled by an ieee 1588 clock r ecovery servo running on an external proce ssor to synthesize ieee 1588 clocks. the 82P33714 requires a system clock for it s reference monitors and other digital ci rcuitry. the frequency accuracy of the syst em clock deter- mines the frequency accuracy of the dplls in free-run mode. the frequency stability of the system clock determines the frequenc y stability of the dplls in free-run mode and in holdover mode; and it af fects the wander generation of the dplls in locked mode. when used with a suitable system clock, dpll1 meets the frequency accuracy, pull-in, hold-in, pullout, noise generation, noise tolerance, tran- sient response, and holdover performance r equirements of the following applications: itu-t g.8262/g.813 eec/sec options 1 and 2 , telcordia gr- 1244 stratum 3 (s3), telcordia gr-253-co re s3 and sonet minimum clock (smc). dpll1 can be configured with a range of selectable filtering band widths from 0.09 mhz to 567 hz. the 17 mhz bandwidth can be us ed to lock the dpll directly to a 1 pps reference. the 92 mhz bandwidth can be used for g.8262/g.813 option 2, or telcordia gr-253-core s3, or smc applica- tions. the bandwidths in the range 1.1 hz to 8.9 hz can be us ed for g.8262/g.813 option 1 applications. the bandwidth of 1.1 hz or 2.2 hz can be used for telcordia gr-1244-core s3 applications. bandwidths abov e 10 hz can be used in jitter attenuation and rate conversion a pplications. dpll2 is a wideband (bw > 25hz) frequency translator that can be used, for example, to convert a recovered line clock to a 1.54 4 mhz or 2.048 mhz synchronization interface clock. for sets applications per itu-t g.8264, dpll1 is configured as an eec/sec to output clocks for the t0 reference point and dpll2 is used to output clocks for the t4 reference point. clocks generated by dpll1 can be passed thr ough apll1 or apll2 which are lc based jitter attenuating analog plls (aplls). the o utput clocks generated by apll1 and apll2 are suitable fo r serial gbe and lower rate interfaces. all 82P33714 control and status registers are accessed through an i2 c slave, spi or uart interface. for configuring the dplls, apll1 and apll2, the i2c master interface can automatically load a configuration from an external eeprom after reset.
82P33714 short form data sheet revision 1 10/20/14 3 synchronous equipment timing source for synchronous ethernet functional block diagram figure 1. functional block diagram control and status registers outdiv outdiv i2c slave, spi, uart jtag i2c master reference monitors reference selection frac-n input dividers sys pll apll1 apll2 outdiv outdiv outdiv dpll1 (t0) out3 (p/n) out4 (p/n) out5 (p/n) out6 (p/n) out7 system clock los0 / xo_freq0 los1 / xo_freq1 los2 / xo_freq2 los3 ex_sync module in3(p/n) in4(p/n) in1(p/n) in2(p/n) in5 in6 frsync_8k_1pps mfrsync_2k_1pps outdiv out1 outdiv out2 outdiv outdiv out9 out10 dpll2 (t4) outdiv out8
82P33714 short form data sheet synchronous equipment timing source for synchronous ethernet 4 revision 1 10/20/14 1 pin assignment figure 2. pin assignment (top view) 8xxxxxx 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 82P33714 vdda vdda vdda vdda vdda osci vc2 tms trstb tdi tck tdo vdda vdda vc1 xo_freq0/los0 xo_freq1/los1 xo_freq2/los2 vddao vssao out4_pos out4_neg vddao vssao out3_pos out3_neg vdddo in1_pos in1_neg in2_pos in2_neg in3_neg in3_pos out2 vdddo out1 in6 vddd_1_8 sdo/i2c_sda/uart_tx clke/i2c_ad1 cs/i2c_ad0 sclk/i2c_scl mpu_mode0/i2cm_sda mpu_mode1/i2cm_scl sdi/i2c_ad2/uart_rx rstb frsync_8k_1pps mfrsync_2k_1pps vddd_1_8 in4_neg vddd in5 in4_pos dpll2_lock vdddo out7 vdddo out8 ms/sl out10 vddao vddao out5_pos out5_neg out6_neg vddd int_req sonet/sdh/los3 out9 out6_pos ic dpll1_lock
82P33714 short form data sheet revision 1 10/20/14 1 synchronous equipment timing source for synchronous ethernet 1 pin description table 1: pin description pin no. name i/o type description global control signal 6osciicmos osci: crystal oscillator system clock a clock provided by a crystal oscillator is input on this pin. it is the system clock for the device. the oscillator frequency is selected via pins xo_freq0 ~ xo_freq2 58 ms/sl i pull-up cmos ms/sl: master / slave selection this pin, together with the ms_sl_ctrl bit, controls whether the device is configured as the master or as the slave. the signal level on this pin is reflected by the master_slave bit. 59 sonet/sdh/ los3 i pull-down cmos sonet/sdh: sonet / sdh frequency selection during reset, this pin determines the default value of the in_sonet_sdh bit: high: the default value of the in_sonet_sdh bit is ?1? (sonet); low: the default value of the in_sonet_sdh bit is ?0? (sdh). after reset, the value on this pin takes no effect. los3- this pin is used to disqualify input clocks. see input clocks section for more details. 52 rstb i pull-up cmos rstb: reset a low pulse of at least 50 s on this pin resets the device. if loading from an eeprom, the maximum time from rstb de-as sert to have stable clocks is 100ms. if not loading from eeprom the maximum time from rstb de-assert to have sta- ble clocks is 10 ms. 7 8 9 xo_freq0/ los0 xo_freq1/ los1 xo_freq2/ los2 i pull-down cmos xo_freq0 ~ xo_freq2: these pins set the oscillator frequency. xo_freq[2:0] oscillator frequency (mhz) 000 10.000 001 12.800 010 13.000 011 19.440 100 20.000 101 24.576 110 25.000 111 30.720 los0 ~ los2 - these pins are used to disqualify input clocks. see input clocks section for more details. after reset, this pin takes on the operation of los0-los2 input clock and frame synchronization input signal 31 32 in1_pos in1_neg i pecl/lvds in1_pos / in1_neg: positive / negative input clock 1 a reference clock is input on this pin.this pin can also be used as a sync input, and in this case a 2 khz, 4 khz, 8 khz, or 1pps signal can be input on this pin. 33 34 in2_pos in2_neg i pecl/lvds in2_pos / in2_neg: positive / negative input clock 1 a reference clock is input on this pin.this pin can also be used as a sync input, and in this case a 2 khz, 4 khz, 8 khz, or 1pps signal can be input on this pin. 35 36 in3_pos in3_neg i pecl/lvds in3_pos / in3_neg: positive / negative input clock 3 a reference clock is input on this pin.this pin can also be used as a sync input, and in this case a 2 khz, 4 khz, 8 khz, or 1pps signal can be input on this pin. 38 39 in4_pos in4_neg i pecl/lvds in4_pos / in4_neg: positive / negative input clock 4 a reference clock is input on this pin.this pin can also be used as a sync input, and in this case a 2 khz, 4 khz, 8 khz, or 1pps signal can be input on this pin. 37 in5 i pull-down cmos in5: input clock 5 a reference clock is input on this pin.this pin can also be used as a sync input, and in this case a 2 khz, 4 khz, 8 khz, or 1pps signal can be input on this pin. 41 in6 i pull-down cmos in6: input clock 6 a reference clock is input on this pin.this pin can also be used as a sync input, and in this case a 2 khz, 4 khz, 8 khz, or 1pps signal can be input on this pin.
82P33714 short form data sheet synchronous equipment timing source for synchronous ethernet 2 revision 1 10/20/14 output frame synchronization signal 43 frsync _8k_1pps ocmos frsync_8k_1pps: 8 khz frame sync output an 8 khz signal or a 1pps sync signal is output on this pin. 44 mfrsync _2k_1pps ocmos mfrsync_2k_1pps: 2 khz mu ltiframe sync output a 2 khz signal or a 1pps sync signal is output on this pin. output clock 30 28 out1 out2 ocmos out1 ~ out2: output clock 1 ~ 2 25 26 out3_pos out3_neg o pecl/lvds out3_pos / out3_neg: positive / negative output clock 3 this output is set to lvds by default. 21 22 out4_pos out4_neg o pecl/lvds out4_pos / out4_neg: positive / negative output clock 4 this output is set to lvds by default. 71 70 out5_pos out5_neg o pecl/lvds out5_pos / out5_neg: positive / negative output clock 5 this output is set to lvds by default. 68 67 out6_pos out6_neg o pecl/lvds out6_pos / out6_neg: positive / negative output clock 6 this output is set to lvds by default. 65 63 out7 out8 ocmos out7 ~ out8: output clock 7 ~ 8 61 60 out9 out10 ocmos out9 ~ out10: output clock 9 ~ 10 miscellaneous 13 vc1 o analog vc1: apll1 vc output an external rc filter (a resistor in series with a capacitor to ground, and another capacitor in parallel) should be connected to this pin. 1vc2oanalog vc2: apll2 vc output an external rc filter (a resistor in series with a capacitor to ground, and another capacitor in parallel) should be connected to this pin. lock signal 54 dpll2_lock ocmos dpll2_lock this pin goes high when dpll2 is locked 55 dpll1_lock ocmos dpll1_lock this pin goes high when dpll1 is locked microprocessor interface 57 int_req o tri-state cmos int_req: interrupt request this pin is used as an interrupt request. 46 45 mpu_mode1/ i2cm_scl mpu_mode0/ i2cm_sda i/o pull-up cmos/ open drain mpu_mode[1:0]: microprocessor interface mode selection during reset, these pins determine the default value of the mpu_sel_cnfg[1:0] bits as fol- lows: 00: i2c mode 01: spi mode 10: uart mode 11: i2c master (eeprom) mode i2cm_scl: serial clock line in i2c master mode, the serial clock is output on this pin. i2cm_sda: serial data input for i2c master mode in i2c master mode, this pin is used as the for the serial data. table 1: pin description (continued) pin no. name i/o type description
82P33714 short form data sheet revision 1 10/20/14 3 synchronous equipment timing source for synchronous ethernet 47 sdi/i2c_ad2/ uart_rx i pull-down cmos sdi: serial data input in serial mode, this pin is used as the serial data input. address and data on this pin are seri- ally clocked into the device on the rising edge of sclk. i2c_ad2: device address bit 2 in i2c mode, i2c_ad[2:0] pins are the addre ss bus of the microprocessor interface. uart_rx in uart mode, this pin is used as the receive data (uart receive) 48 clke/i2c_ad1 i pull-down cmos clke: sclk active edge selection in serial mode, this pin is an input, it selects the active edge of sclk to update the sdo: high - the falling edge; low - the rising edge. i2c_ad1: device address bit 1 in i2c mode, i2c_ad[2:0] pins are the addre ss bus of the microprocessor interface. 49 cs/i2c_ad0 i pull-up cmos cs : chip selection in serial modes, this pin is an input.a transition from high to low must occur on this pin for each read or write operation and this pin should remain low until the operation is over. i2c_ad0: device address bit 0 in i2c mode, i2c_ad[2:0] pins are the addre ss bus of the microprocessor interface. 50 sclk/i2c_scl i pull-down cmos sclk: shift clock in serial mode, a shift clock is input on this pin. data on sdi is sampled by the device on the rising edge of sclk. data on sdo is updated on the active edge of sclk. the active edge is determined by the clke. i2c_scl: serial clock line in i2c mode, the serial clock is input on this pin. 51 sdo/i2c_sda/ uart_tx i2c_sda i/o pull-up cmos/ open drain sdo: serial data output in serial mode, this pin is used as the serial data output. data on this pin is serially clocked out of the device on the active edge of sclk. i2c_sda: serial data input/output in i2c mode, this pin is used as the input/output for the serial data. uart_tx: in uart mode, this pin is used as the transmit data (uart transmit) jtag (per ieee 1149.1) 14 tms i pull-up cmos tms: jtag test mode select the signal on this pin controls the jtag test performance and is sampled on the rising edge of tck. 15 trstb i pull-up cmos trstb: jtag test reset (active low) a low signal on this pin resets the jtag test port. this pin should be connected to ground when jtag is not used. 16 tck i pull-down cmos tck: jtag test clock the clock for the jtag test is input on this pin. tdi and tms are sampled on the rising edge of tck and tdo is updated on the falling edge of tck. if tck is idle at a low level, all stored-state devices contained in the test logic will indefinitely retain their state. 17 tdi i pull-up cmos tdi: jtag test data input the test data are input on this pin. they are clocked into the device on the rising edge of tck. table 1: pin description (continued) pin no. name i/o type description
82P33714 short form data sheet synchronous equipment timing source for synchronous ethernet 4 revision 1 10/20/14 1.1 recommendations for unused input and output pins 1.1.1 inputs control pins all control pins have internal pul l-ups or pull-downs ; additional resis- tance is not required but can be added for additional protection. a 1k resistor can be used. single-ended clock inputs for protection, unused single- ended clock inputs should be tied to ground. differential clock inputs for applications not requiring the use of a differential input, both *_pos and *_neg can be left floating. though not required, but for additional protection, a 1k resistor can be tied from _pos to ground. 1.1.2 outputs status pins for applications not requiring the use of a status pin, we recommend bringing out to a test point for debugging purposes. single-ended clock outputs all unused single-ended clock outputs can be left floating, or can be brought out to a test point for debugging purposes. differential clock outputs all unused differential outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. 18 tdo o tri-state cmos tdo: jtag test data output the test data are output on this pin. they are clocked out of the device on the falling edge of tck. tdo pin outputs a high impedance signal except during the process of data scanning. power & ground 2, 3, 4, 5, 10 11, 12 vdda power - vdda : analog core power - +3.3v dc nominal 20, 24, 69, 72 vddao power vddao : analog output power - +3.3v dc nominal 27, 29, 64, 66 vdddo power vdddo : digital output power - +3.3v dc nominal 40, 62 vddd power vddd : digital core power - +3.3v dc nominal 42, 53 vddd_1_8 power vddd_1_8 : digital core power - +1.8v dc nominal 19,23 vssao ground vssao : ground 73 (e_pad) vss ground - vss : ground other 56 ic - - ic : internal connection internal use. this pin must be left open for normal operation. table 1: pin description (continued) pin no. name i/o type description
82P33714 short form data sheet revision 1 10/20/14 5 synchronous equipment timing source for synchronous ethernet package dimensions figure 1. 72-pin qfn package outline page 1 (sawn option)
82P33714 short form data sheet synchronous equipment timing source for synchronous ethernet 6 revision 1 10/20/14 figure 2. 72-pin qfn package outline page 2 (sawn option)
82P33714 short form data sheet revision 1 10/20/14 7 synchronous equipment timing source for synchronous ethernet figure 3. 72-pin qfn package recommended land pattern
82P33714 short form data sheet synchronous equipment timing source for synchronous ethernet 8 revision 1 10/20/14 ordering information "g" after the two-letter package code denot es pb-free configuration, rohs compliant. revision history table 2: ordering information part/order number package temperature 82P33714anlg 72-pin qfn -40 o to +85 o c rev. date description of change
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